Chips, from a spec to signoff.

Open-source EDA is now good enough to ship real silicon, but the toolchain is wide, fragmented and unforgiving — a single RISC-V core can need 15+ invocations across 8 tools, each with its own flags and log format. Xenon puts a team of Claude Code agents in charge of that toolchain: they read synthesis reports, parse timing violations, and edit RTL to fix them. A checkpointed step pipeline keeps every artifact reproducible, and an MCP server exposes the whole flow to agentic IDEs.

AEGIS (Adaptive Engine for Guarded Integrated Systems) is a three-domain SoC built for hard real-time control in safety-critical domains — airborne (DO-254 DAL-A) and automotive (ISO 26262 ASIL-D). A real-time control domain (RV32IMACF + Xdrone) runs at 240 MHz with TCLS 2oo3 lockstep voting; an application domain (RV64GCV, out-of-order) and a security domain (RV32E with PMP + root of trust) sit on the same safety interconnect. The design prioritises deterministic timing, fault detection, and certification traceability.

Azmuth extends the standard RV32IMC instruction set with custom Xcew instructions for edge AI. An Expression-ML pipeline evaluates exp/ln/sub with a memoization cache and DAG-based common-subexpression elimination; a spiking-neural-network array uses time-to-first-spike encoding with STDP learning; and a ReRAM non-volatile-memory controller adds wear-leveling and ECC. Deterministic, constant-time policy execution guards against timing side-channels, while per-tile power orchestration handles sleep/wake and body-bias control.