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AI Lab

Autonomous agents for the hardest engineering.

The AI Lab turns frontier models into dependable operators. Our agents own hard, multi-tool workflows end to end — reading synthesis reports and fixing RTL, running a MISRA compliance fix-loop, or orchestrating an entire chip flow. Everything is verification-first: agents show their work, respect guardrails, and hand control back cleanly.

Multi-agent orchestrationTool-use & verification loopsAgentic EDA & complianceEdge AI acceleration
AI Lab logo
3
projects in this lab
MCP
agent-ready from any IDE
9
tracked milestones
AI
lab designation

3 projects underway

Xenon

In Development

The agentic silicon compiler.

Open-source EDA is now good enough to ship real silicon, but the toolchain is wide, fragmented and unforgiving — a single RISC-V core can need 15+ invocations across 8 tools, each with its own flags and log format. Xenon puts a team of Claude Code agents in charge of that toolchain: they read synthesis reports, parse timing violations, and edit RTL to fix them. A checkpointed step pipeline keeps every artifact reproducible, and an MCP server exposes the whole flow to agentic IDEs.

161
tests passing
10+
EDA tools orchestrated
RTL→GDS
flow

What makes it different

  • Agents read synthesis & timing reports, then edit RTL to close violations
  • Reproducible Docker sandbox — every run is checkpointed and diffable
  • MCP server exposes the flow to any agentic IDE
  • Targets tape-out-proven SkyWater 130 & GF 180 PDKs

Stack

VerilatorYosysOpenROADOpenLANEcocotbnextpnrGTKWave

Also in

Agentic EDARTL→GDSIIOpenLANEMCPClaude Code

Azmuth

Research

A neuro-inspired RISC-V accelerator for edge AI.

Azmuth extends the standard RV32IMC instruction set with custom Xcew instructions for edge AI. An Expression-ML pipeline evaluates exp/ln/sub with a memoization cache and DAG-based common-subexpression elimination; a spiking-neural-network array uses time-to-first-spike encoding with STDP learning; and a ReRAM non-volatile-memory controller adds wear-leveling and ECC. Deterministic, constant-time policy execution guards against timing side-channels, while per-tile power orchestration handles sleep/wake and body-bias control.

RV32IMC
base ISA
Xcew
custom ISA
EML·SNN·NVM
AI blocks

What makes it different

  • Expression-ML pipeline with memoization + CSE via a DAG
  • Spiking neural network: LIF neurons, TTFS encoding, STDP learning
  • ReRAM NVM controller with wear-leveling and ECC
  • Constant-time policy execution + per-tile power orchestration

Stack

VerilogRISC-VReRAMSNN

Also in

RISC-VAI AcceleratorSNNEdge AIVerilog

Maisha

Open Source

Open-source MISRA / CERT / BARR-C compliance for embedded C.

Maisha is the free, vendor-neutral alternative to the paid compliance workflow that tools like Polyspace, Helix QAC and Coverity sell: the agentic fix loop, verification gate, deviation and audit-evidence workflow, and author-time guidance. It runs on free engines (cppcheck + clang-tidy) or layers on top of a qualified engine you already own via SARIF. It is a workflow orchestrator and audit-trail layer — not a qualified detection engine, and honest about it. Named for the Swahili word for 'life' — because this is the code that flies planes and runs medical devices.

3
standards
v0.3.1
release
MIT
license

What makes it different

  • MISRA C:2012, BARR-C:2018 and CERT C compliance workflows
  • Agentic fix loop + verification gate + deviation & audit evidence
  • Runs on free engines (cppcheck + clang-tidy) or a qualified one via SARIF
  • Install with `pipx install maishac` — usable from any agentic IDE via MCP

Stack

Pythoncppcheckclang-tidySARIFMCP

Also in

MISRA CCERT CStatic AnalysisMCPMIT

Have a hard problem worth freezing time over?

Whether it's silicon, capital, or research at the edge of what's possible — we'd love to hear what you're building.