Winter Labs is organized into specialized labs. Each owns a distinct mission — from taping out chips to open-sourcing the tools that make it possible — while sharing research and infrastructure.
Chips, from a spec to signoff.
We design real silicon on the open-source EDA stack — RISC-V processor IP and an agentic compiler that carries a chip from spec to tapeout.
Autonomous agents for the hardest engineering.
We build agentic systems that own real toolchains — designing chips, enforcing compliance, and accelerating AI at the edge, not just autocompleting.
Machine learning that survives the real world.
We do applied ML research aimed at deployment — models that generalize across datasets and run on constrained edge hardware, not just benchmarks.
Mission systems for the sky.
We build software-defined avionics and mission systems — portable landing aids and flight-path monitoring for demanding, safety-critical operations.
Software we build in the open, for everyone.
We open-source the tooling we build internally — vendor-neutral alternatives to expensive proprietary workflows, free for the whole community.
New frontiers are forming.
We spin up new labs whenever a problem is big enough to deserve one. Something new is condensing — stay close.
A running index of the projects underway across every lab.
The agentic silicon compiler.
Turn a Markdown chip spec into verified, place-and-routed silicon on the open-source EDA stack — orchestrated by Claude Code.
Xenon owns a wide, fragmented toolchain inside a reproducible Docker sandbox and collapses a 15+ invocation, 8-tool flow into a conversation.
Safety-certifiable RISC-V processor IP.
A certifiable RV32IMACF core for hard real-time control — DO-254 DAL-A flight and ISO 26262 ASIL-D automotive, at 240 MHz on 130nm.
A three-domain SoC on a unified safety interconnect with lockstep voting, ECC memory, and certification traceability.
A neuro-inspired RISC-V accelerator for edge AI.
The Xcew processor — RV32IMC extended with custom instructions for neural inference, expression ML, and non-volatile memory.
Custom Xcew extensions pack expression-ML, spiking neural networks, and a ReRAM controller onto a deterministic RISC-V core.
Open-source MISRA / CERT / BARR-C compliance for embedded C.
The free, vendor-neutral alternative to Polyspace, Helix QAC and Coverity's paid compliance workflow — driven from any agentic IDE via MCP.
The compliance-workflow layer for MISRA C:2012, BARR-C:2018 and CERT C, running on free engines or layered on a qualified one via SARIF.
Cross-dataset ECG arrhythmia classification for the edge.
A lightweight deep-learning model for single-lead ECG risk triage that generalizes across datasets and runs on ARM Cortex-A72.
Research into cross-dataset generalization for ECG classification, optimized for real edge deployment rather than benchmark accuracy.
Transportable electronic glide-path for hill helipads.
A software-defined portable landing aid giving IAF helicopter crews a stable glide path into steep, high-altitude helipads in poor visibility — with independent ground-side monitoring.
Guidance plus independent ground-side verification for steep, high-altitude helicopter approaches — developed under iDEX DISC 12.
Whether it's silicon, capital, or research at the edge of what's possible — we'd love to hear what you're building.